ระบบคืนสัญญาณ บีพีเอสเค คิวพีเอสเค เอ็มพีเอสเค แบบเฟสเดียว ลูปเดียว บนหลักการเฟสล็อคลูปในเทคโนโลยีซีมอส

Abstract

A general single-phase/single-loop PLL-based m-PSK demodulator is described. The demodulator employs a rising-edge RS flip-flop as a phase detector because of its linear <phase difference>/<average output voltage> over a 0˗2π phase difference. This flip-flop characteristic helps simplify the phase controller design and make it truly modular. The phase controller basically explores a sub-ranging/re-scaling technique similar found in a typical ADC converter. The proposed principle has been verified with discrete-component implementation around 74HCT4046 for demodulating BPSK, QPSK and 8-PSK signals. The modulator prototypes operate under a single supply of 5V achieving a maximum data rate of 40kbps at a carrier frequency around 120-kHz. The discrete-component experimental comparison with a widely-used Costas-Loop BPSK demodulator suggests that the proposed structure offers a competitive performance. The single-phase BPSK and QPSK demodulators based on the proposed technique have also been designed and fabricated in a UMC 0.18-m standard digital CMOS process. The rising-edge RS flip-flop has been constructed from a basic NOR-gate static structure equipped with a delayed-type edge detector. The core of CMOS phase controller employs a simple voltage level shifter incorporating a passive poly-silicon resistor, a constant DC current source and transmission-gate switches where สำ a voltage gain is provided by a resistive source-degenerated amplifier. The demodulator prototypes operate from a single supply of 1.8V. The three-stage voltage-controlled ring oscillator can be tuned from 5 to 150MHz. With a carrier frequency of 60 MHz, the BPSK and QPSK demodulators achieved maximum data rates of 25Mbps and 24Mbps respectively while consuming 1.68mW and 1.92mW. At 10-Mbps data, the BPSK and QPSK demodulators deliver bit-error rates (BER) of 5×10-10 and 6.5×10-10, respectively at the signal-to-noise ratio (SNR) of 16dB for both cases. At the maximum

data rates, these BERs have been increased to 3.5×10-7 and 5.5×10-7 for BPSK and QPSK demodulators where the energy per bit figures were at 67 and 80 pJ, respectively.