โพรเซสเซอร์ร่วมกำลังไฟต่ำสามารถปรับเปลี่ยนโครงสร้างได้แบบไดนามิก

Abstract

ASIC (application specific integrated circuit) processor dissipates a low power consumption and is able to perform at a high speed. Unfortunately, ASIC production costs every high expense. Therefore, it is not suitable for a prototype or a small volume product. A programmable device becomes a good choice. Reconfigurable hardware will give a better performance and flexibility. This research work proposes Dynamically Reconfigurable Datapath (DRD) which is to reconfigure a part of FPGA while the processor of FPGA is still working. This reconfigurable datapath can increase resource utilization and sharing when image or video processing applications are applied. Thus it also increases the energy efficiency. This dynamically reconfigurable co-processor employs clock-gating technique. We also introduce the concept of computer aided software for dynamic reconfigurable design which is able to reduce an overhead of place and route algorithm. This dynamie reconfigurable co-processor can be programmed and used up to four parallel functional units (FUs). The design was implemented on FPGA XC3SD1800. The simulation result shows that the co-processor can run at 59 MHz and dissipated 34.64 mW which can complete FIR 20-tap within 0.339 us. The preliminary result of task placement suggests that both first fit and best fit algorithms give the similar speed and the number of task that cannot be placed. Therefore, we choose first fit algorithm in our EDA tool because of the lower list of the empty space.